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SUMMIT
MICROELECTRONICS, Inc. Quad 10-Bit Nonvolatile DACPOTTM
FEATURES
l Four Programmable 10-Bit Nonvolatile DACs M INL 1LSB, DNL 1LSB, 1024 Steps Each l Power on Recall at any Value l Parallel or Independent Operation of DACs l Excellent Temperature Stability - 15ppm/0C M Industrial Temperature range l 1.25V Precision Voltage Reference l I2C Serial Bus Interface l Very Small QFN package M 5mm square APPLICATIONS l Laser bias/modulation current adjustment l Power supply trimming/margining l Potentiometer replacement
SMP9410
Preliminary Information
1 see last page
INTRODUCTION
The SMP9410 is a quad 10 bit (1024 steps) Non Volatile D-to- A converter or DACPOTTM. The device will recall any analog voltage on power up, making it ideal for high accuracy and temperature stable calibration purposes and can operate from a single +2.7V to +5.5V supply. Internal precision buffers swing rail-to-rail with an input voltage range from ground to the positive supply. The part integrates four 10-bit DACs and associated circuits: an enhanced unity gain operational amplifier output, a 10-bit volatile data latch, a 10-bit nonvolatile data register, and I2C bus industry standard 2-wire serial interface. The SMP9410 is available in a very small 5mm square Quad Flat package with No leads (QFN) for small form factor designs. Programming of configuration, control and calibration values by the user can be simplified with the interface adapter and Windows GUI software obtainable from Summit Microelectronics.
FUNCTIONAL BLOCK DIAGRAM
VDD 24
100K 3 plcs
13 VREFH0
NONVOLATILE REGISTER
CONFIGURATION REGISTER A0 A1 3
VOLATILE CONTROL REGISTER
10-BIT DAC
19 VOUT0
A2 28 SDA SCL CS 4
100K
INTERFACE & CONTROL LOGIC
2
14 VREFL0 11 VREFH1
NONVOLATILE REGISTER
VOLATILE CONTROL REGISTER
5
100K
10-BIT DAC
17 VOUT1
6
12 VREFL1
SMP9410
1.25VREF 20
9
VREFH2
NONVOLATILE REGISTER
VOLATILE CONTROL REGISTER
PRECISION REFERENCE
Note: Pin numbers are for the QFN.
10-BIT DAC
16 VOUT2
10 VREFL2 7 VREFH3
VDD
NONVOLATILE REGISTER VOLATILE CONTROL REGISTER
10-BIT DAC 15 VOUT3
100K
100K
MUTE#_CH 22 MUTE# 23
8 VREFL3
25 GND
2056 BD
(c)SUMMIT MICROELECTRONICS, Inc., 2002 * 300 Orchard City Dr., #131 * Campbell, CA 95008 * Phone 408-378-6461 * FAX 408-378-6586 * www.summitmicro.com
Characteristics subject to change without notice
2056 2.0 10/04/02
SMP9410
Preliminary Information
DEVICE OPERATION
INTRODUCTION The device has four 10-Bit digital to analog converters that are comprised of a resistor network that converts a digital input into an equivalent analog output voltage in proportion to the applied reference voltages. The voltage differential between each VREFL and VREFH input pair sets the range and full-scale output voltage for their respective DAC. Each DAC has a 10-Bit nonvolatile register that can hold a `set-and-forget' value that can be recalled whenever the device is powered-on. Each DAC has a 10-Bit volatile register that holds the current digital value. The register can be set to any value by the serial interface; commanded to load the zero scale value, full scale value or mid-scale value; or can recall a preset value stored in a nonvolatile register. The device also has a nonvolatile configuration register that is accessible over the 2-wire bus. The configuration register is used to select the device type identifier and the DAC power-on state. The device uses the industry standard I2C 2-wire serial protocol. The bus is designed for two-way, two-line serial communication between different integrated circuits. The two lines are the SCL (serial clock) and SDA (serial data). Both lines should be pulled up to the positive supply through a resistor. The protocol defines devices as being either Masters or Slaves. The SMP9410 will always be a Slave because it does not initiate any communications or provide a clock output.
PIN CONFIGURATION TOP VIEW
QFN
GND VDD MUTE# MUTE#_CH
TQFP
NC NC NC NC NC NC GND VDD MUTE# MUTE#_CH NC NC 48 47 46 45 44 43 42 41 40 39 38 37
NC
NC
A2
NC
8 9 10 11 12 13 14
A1 A0 SDA SCL CS VREFH3
1 2 3 4 5 6 7
21 20 19 18 17 16 15
NC
1.25VREF VOUT0
NC
VOUT1 VOUT2 VOUT3
NC A2 NC NC A1 A0 NC SDA SCL CS NC NC
1 2 3 4 5 6 7 8 9 10 11 12
36 35 34 33 32 31 30 29 28 27 26 25
NC NC 1.25VREF NC VOUT0 NC VOUT1 VOUT2 NC VOUT3 NC NC
28 27 26 25 24 23 22
VREFL3 VREFH2 VREFL2 VREFH1 VREFL1 VREFH0 VREFL0
VREFH3 VREFL3 VREFH2 VREFL2 VREFH1 VREFL1 VREFH0 VREFL0 NC NC NC NC
13 14 15 16 17 18 19 20 21 22 23 24
2056 PCon-L
2056 PCon-F
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SMP9410
Preliminary Information
PIN DESCRIPTIONS
Pin # 1,18,21,26,27 3,2,28 4 5 6 13,11,9,7 14,12,10, 8 19,17,15,16 20 22 Type Pin N ame NC I I/O I I I I O O I NC A 0, A 1, A 2 SD A SC L CS Pin D escription
Note: Pin numbers are from LPCC.
No C onnect. NC pi ns are not connected The address i nputs for the seri al i nterface logi c. Setti ng them hi gh or low wi ll determi ne the devi ce' s bus address that i s contai ned wi thi n the seri al bus data stream. These pi ns have i nternal 100K9 pull-up resi stors to VDD The bi di recti onal pi n used to transfer data i n and out of the devi ce. The seri al i nterface clock. It i s used to clock the data i n and out. Thi s pi n has an i nternal 100K9 pull-up resi stor to VDD C hi p Select i nput (VIH = selected) Thi s pi n has an i nternal 100KK9 pull-up resi stor to VDD
VREFH0, VREFH1, The hi gher of the voltage reference i nputs. VREFH must be equal to or less VREFH2, VREFH3 than VDD and greater than VREFL. VREFL0, VREFL1, The lower of the voltage reference i nputs. VREFL must be equal to or greater VREFL2, VREFL3 than ground and less than VREFH. VOUT0, VOUT1, VOUT2, VOUT3 1.25VREF MUTE#_C H The voltage output of the D AC s. It i s buffered by a uni ty-gai n follower that can slew up to 1V/s. A 1.25V output reference voltage. The MUTE#_C Hoi ce i nput sets the VOUT levels when MUTE# i s asserted low (MUTE_C H# hi gh = VREFH, MUTE_C H# low = VREFL). Thi s pi n has an i nternal 100K9 pull-up resi stor to VDD Forces the VOUT levels to be equal to ei ther the VREFH or VREFL level, accordi ng to the value of MUTE#_C H (VIL = mute). Thi s pi n has an i nternal 100K9 pull-up resi stor to VDD Power supply i nput. Power supply return.
23 24 25
I PWR PWR
MUTE# V DD GND
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SMP9410
Preliminary Information
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ......................... -55C to 125C Storage Temperature .............................. -65C to 150C Terminal Voltage with Respect to GND: VDD ................................ -0.3V to 6.0V All Others ....................... -0.3V to 6.0V Output Short Circuit Current.............................100mA Lead Solder Temperature (10 secs).....................300 C Junction Temperature.........................................150C ESD Rating per JEDEC.....................................2000V Latch-Up testing per JEDEC..........................+/- 100mA
Note * - The device is not guaranteed to function outside its operating rating. Stresses listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
RECOMMENDED OPERATING CONDITIONS Temperature ........................................... -40C to 85C Voltage .................................................... 2.7V to 5.5V Package Thermal Resistance GJA GJC 48 Pin TQFP = 80C/W, 28 Pin QFN= 80C/W 48 Pin TQFP = 40C/W, 28 Pin QFN= 32C/W
Moisture Classification Level 1 (MSL 1) per J-STD- 020
RELIABILITY CHARACTERISTICS Data Retention..........................................100 Years Endurance........................................100,000 Cycles
DC OPERATING CHARACTERISTICS
(Over Recommended Operating Conditions; Voltages are relative to GND) Symbol Power Power supply current NV write VDD = 5.5V NV write VDD = 2.7V VDD = 5.5V; Excluding current through DACs VDD = 2.7V; Excluding current through DACs VDD = 5.5V; Total current including DACs VDD = 2.7V; Total current including DACs 2.7 0.7 x VDD 0.3 x VDD IOL = 3mA VIN = 0 to VDD VOUT powered down in high impedance mode Number of NV store operations NV data retention 1 x 106 100 100 10 0.4 3 3 1 1 1 1 5.5 mA mA mA mA mA mA V V V V A A NV stores Years
2056 Elect TableA
Parameter
Condition
Min.
Typ.
Max.
Units
IDD
Standby or quiescent
Power down
VDD VIH VIL VOL ILI ILO WEND tDR
4
Supply voltage SDA, SCL, CS, MUTE#, MUTE#_CH, A0, A1, A2 SDA Input leakage Output leakage Write endurance Data retention
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SMP9410
Preliminary Information
DC OPERATING CHARACTERISTICS (CONTINUED)
(Over Recommended Operating Conditions; Voltages are relative to GND)
Symbol Parameter Condition Min. Typ. Max. Units
Static Performance N INL DNL VZSE VFS TCV Resolution Relative Accuracy Differential nonlinearity Zero scale error Full scale voltage Full scale temperature coefficient Offset error Gain error Matching Performance Linearity matching error Analog Output IOUT LDREG CL BW THD Output current@Half Scale Load regulation @ halfscale Capacitive load Dynamic Characteristics -3dB bandwidth Total harmonic distortion Channel-to-channel isolation Digital cross-talk Reference Voltages VREFH VREFL 1.25VREF VREFH > VREFL VREFL < VREFH GND 1.2 1.25 1.3 VDD V V V R = 10k VA = 1VRMS, f = 1kHz f = 1kHz, VIN = 100mVPP on VREFH 100 0.08 -60 -60 kHz % dB dB Data = 200HEX, VOUT = 3LSB, VREFHX=VDD=5V Data = 200HEX, RL = 1k to No oscillation -0.25 1 500 +0.25 3 mA LSB pF 1 LSB -0.2 -0.5 VREFH = 5V, VREFL = 0V VREFH = 5V, VREFL = 0V Guaranteed monotonic Data = 000HEX Data = 3FFHEX 15 +0.2 +0.5 10 -2 -1 0 1 0.5 2 1 15 VREFH -1LSB Bits LSB LSB mV V ppm %VFS %
2056 Elect TableB
SUMMIT MICROELECTRONICS, Inc.
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SMP9410
Preliminary Information
AC OPERATING CHARACTERISTICS
(Over Recommended Operating Conditions)
Symbol fSCL tLOW tHIGH tBUF tSU:STA tHD:STA tSU:STO tAA tDH tR tF tSU:DAT tHD:DAT TI tWR
Parameter SCL clock frequency Clock low period Clock high period Bus free time (1) Start condition setup time Start condition hold time Stop condition setup time Clock edge to valid output Data Out hold time SCL and SDA rise time (1) SCL and SDA fall time (1) Data In setup time Data In hold time Noise filter SCL and SDA (1) Write cycle time
Conditions
Min. 0 4.7 4.0
Max. 100
Units kHz s s s s s s
Before new transmission
4.7 4.7 4.0 4.7
SCL low to valid SDA (cycle n) SCL low (cycle n+1) to SDA change
0.3 0.3
3.5
s s
1000 300 250 0 Noise suppression 100 5
ns ns ns ns ns ms
2056 Table01
Note (1) These values are guaranteed by design. Refer to the timing diagram in Figure 4.
Table 1. Data/Clock Timing
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SMP9410
Preliminary Information
DEVELOPMENT HARDWARE & SOFTWARE
PROGRAMMING CONNECTION The end user can obtain the Summit SMX3200 programming system for device prototype development. The SMX3200 system consists of a programming Dongle, cable and Windows GUI software. It can be ordered on the website or from a local representative. The latest revisions of all software and an application brief describing the SMX3200 is available from the website (www.summitmicro.com). The SMX3200 programming Dongle/cable interfaces directly between a PC's parallel port and the target application. The device is then configured on-screen via an intuitive graphical user interface employing drop-down menus. The Windows GUI software will generate the data and send it in I2C serial bus format so that it can be directly downloaded to the SMP9410 via the programming Dongle and cable. An example of the connection interface is shown in Figure 1.When design prototyping is complete, the software can generate a HEX data file that should be transmitted to Summit for approval. Summit will then assign a unique customer ID to the HEX code and program production devices before the final electrical test operations. This will ensure proper device operation in the end application.
Top view of straight 0.1" x 0.1" closed side connector SMX3200 interface Pin 10, Reserved Pin 8, Reserved Pin 6, Reserved Pin 4, SDA Pin 2, SCL Pin 9, 5V Pin 7, 10V Pin5, Reserved Pin3, GND Pin 1, GND
Positive Supply VDD SMP9410 GND
SDA SCL
10 8 6 4 2
9 7 5 3 1
C1 0.01F
Negative Supply
2056 Fig06
Figure 1. SMX3200 Programmer connections for the SMP9410.
APPLICATIONS INFORMATION
+5V 24 0.01mF V DD V REFH 0 13 19 V OU T0 0.01mF 3 O ptional Address Biasing 2 A1 28 23 User O ptions 22 A2 M UTE # M UTE #_C H V REFL 1 12 V REFH 1 V OU T1 V REFL 0 14 11 V1 17 0.01mF V0
10 mF
O ptional
A0
S M P 9410
S DA S CL CS 4 S DA 5 S CL 6 CS 25 Com m on G ND 1.25V REF 20 0.1mF G ND
V REFH 9 2 16 V O U T2 0.01mF V REFL 2 10
V2
7 V REFH 3 15 V O U T3
V3
V REFL 3
0.01mF 8
28 Lead QF N P in N um bering
Figure 2. Applications Schematic. Additional bypass capacitors may be needed in noisy environments. The VREFH and VREFL pins can be tied to VDD or GND or as specified in the pin descriptions. For optimum performance, all capacitors should be placed as close as possible to the SMP9410 Pins
SUMMIT MICROELECTRONICS, Inc. 2056 2.0 10/04/02
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SMP9410
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
ACCESSING THE DACS Data transfers are initiated when a Master issues a Start condition, which is a high to low transition on SDA while SCL is high (see Figure 3). The Start is immediately followed by an eight bit transmission: bits 7 through 1 comprise the device type identifier and device bus address; bit 0 is the Read/Write bit indicating the action to follow. If the intended device receives the byte and recognizes its address it will return an Acknowledge during the 9th clock cycle. Some data transfers will be concluded with a Stop condition, which is a low to high transition on SDA while SCL is high. Note: a Stop condition must be performed for all nonvolatile Write operations. Timing for all I2C operations are summarized in Figure 4 and Table 1. The default device type identifier for addressing DACs is 0101BIN. In order to accommodate more than eight devices on a single bus the device type identifier can be modified by the end user by writing to the configuration registers. (See Table 2). A0, A1 and A2 are the address inputs. When addressing the nonvolatile or configuration registers, theaddress inputs distinguish which one of eight possible devices sharing the common bus is being addressed. Setting them high or low will determine the device's bus address that is contained within the serial bus data stream. Command Structure The command structure is illustrated in Table 2. Of special note is the ability to write individually to any of the four DACs, or to all of them. The first five commands are three bytes in length and can either be volatile or nonvolatile DAC writes.
START Condition SCL
STOP Condition
SDA In
2056 Fig01
Figure 3. START and STOP Timing
tR
tF
tHIGH
tLOW
SCL
tSU:STA tHD:DAT tSU:DAT tSU:STO
tHD:STA
tBUF
SDA In
tAA
tDH
SDA Out
2056 Fig02
Figure 4. I2C Data/Clock Timing
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SMP9410
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
ACK and NACK A device that is receiving data will respond with an Acknowledge by pulling the SDA line low (ACK) after each byte is transmitted. The transmitting device will recognize this and continue to transmit. When the Master has received the data it expects it will hold the SDA line high (NACK) and the transmitting device will end transmission. Sequence The sequence is to issue a Start, followed by the device type and bus address with the Read/Write bit set to zero. The device will respond with an Acknowledge and the Master will then issue the command and follow-on data. In Figure 5 the Write is to DAC1 where the command = 1001BIN; D9 and D8 are the MSBs of the DAC value being written. The device will then respond with an Acknowledge followed by the Master writing the last eight bits. If no Stop is generated after the device Acknowledge the Write is only to the register. If the device Acknowledge is followed by a Stop the data is written to both the DAC register and to the nonvolatile register.
R/ W 0101 AAA 0 210 A C K
Reading the Device Reading the DACs requires setting the R/W bit to one. Then the host supplies clocks and the device will output data as shown in Figure 6. Configuration Register The SMP9410 can be configured by the end user or by Summit prior to shipment (see Programming Information). Reading the configuration register can also be performed if it has not already been locked. See Figure 7. There is one configuration register and it is accessed through the serial interface using 1001BIN as the device type address, consequently the DAC address should never be set to 1001BIN. The register is shown in Table 3.
Nonvolatile Write Only
Master SDA Slave
Command Data Byte DD 1001x x98 A C K DDDDDDDD 76543210 A C K
S T O P
2056 Fig03
Figure 5. DAC1 Write Operation (see Table 2)
Data from Master
DAC
Data to Master
A C K xx x x x xDD 98 A C K DDDDDDDD 76543210
Master SDA Slave
0101
R/ W AAA 1 210 A C K 1001xxxx
N A C K
S T O P
2056 Fig04
Figure 6. Read DACs
Optional
Master SDA Slave
1001
R/ W AAA 1 210 A C K
Configuration Data Byte CCCCCCCC 76543210 A C K
S T O P
2056 Fig05
Figure 7. Configuration Register (see Table 3)
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SMP9410
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
MSB D7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
D6 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
D5 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0
D4 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 0
D3 x x x x x x x x x x x x x x x x
D2 x x x x x 0 0 0 0 1 0 0 0 0 1 x
D1 D9 D9 D9 D9 D9 0 0 1 1 x 0 0 1 1 x x
LSB D0 D8 D8 D8 D8 D8 0 1 0 1 x 0 1 0 1 x x
Command Write DAC0 Write DAC1 Write DAC2 Write DAC3 Write all DACs Recall E2 to DAC0 Recall E2 to DAC1 Recall E2 to DAC2 Recall E2 to DAC3 Recall E2 to all DACs PD DAC0 PD DAC1 PD DAC2 PD DAC3 PD all DACs PU all DACs
Function
Volatile with no stop, nonvolatile with stop
Recall E2 to DACs
Power down DACs (see Table 3)
Power up all DACs
2056 Table02
Table 2. Command Structure
MSB C7
C6
C5
C4
C3
C2 x x 0 0 1 1
C1 x x 0 1 0 1
LSB C0 0 1
Function Configuration register accessible Configuration register locked Power on recall: DACs set to all 0s Power on recall: DACs set to all 1s Power on recall: DACs set to mid scale Power on recall: DACs set to NV register
x x x x x
0 1 PDA3* PDA2* PDA1* PDA0* x x x
x
At power down VOUT = low impedance At power down VOUT = high impedance Programmable Device Type Identifier for DAC addressing
2056 Table03
* Note: Never set the Programmable Device Type Identifier for DAC addressing to 1001BIN. The Slave address for the configuration register is 1001BIN, and a collision will occur on the I2C bus. Note: All parts are normally shipped with the Configuration Register locked with setting 5Fh (01011111). Unlocked user configurable parts are available on a special order basis. Contact Summit.
Table 3. Configuration Register
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2056 2.0 10/04/02 SUMMIT MICROELECTRONICS, Inc.
SMP9410
Preliminary Information
PACKAGES
48 P IN T Q F P P AC K AG E
0 .3 5 4 (9 .0 0 ) 0 .2 7 6 (7 .0 0 ) BSC In c h e s (M illim e te rs )
(A )
B S C (B )
0 .0 2 (0 .5 )
BSC
0.0 0 7 - 0 .0 1 1 (0 .1 7 - 0 .2 7 )
D E T AIL "A"
(B ) (A)
R e f J e d e c M S -0 2 6
0 .0 3 7 - 0 .04 1 0 .9 5 - 1 .05 P in 1 In d ic a to r 0 .0 3 9 (1 .0 0 )
R ef
0 .0 4 7 M A X. (1 .2 )
0 o M in to 7o Max
A
B
0.0 0 2 - 0 .0 0 6 (0 .0 5 -0 .1 5 )
0 .0 1 8 - 0 .03 0 (0 .4 5 - 0 .75 )
D E T AIL "B "
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SMP9410
Preliminary Information
PACKAGES (CONTINUED)
28 PIN QFN PACKAGE
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SMP9410
Preliminary Information
ORDERING INFORMATION
SMP9410 Base Part Number
N Package N = QFN F = TQFP
2056 Tree
PART MARKING
S u m m it P a rt N u m b e r
SUMMIT
Status Tracking Code (Blank, MS, ES, 01, 02,...) (Summit Use)
Sum mit Part Number
S U M M IT S M P 9410 F An n n xx
S tatus T racking C ode (Blank , M S , ES, 01, 02,...) (Sum m it U se)
SMP9410N xx Annn AYYW W
AY Y W W
Pin 1
Date Code (YYW W )
P in 1
D ate C ode (YYW W )
Lot tracking code (Summit use)
Lot tracking code (Sum m it use)
Drawing not to scale
Part Number suffix
D raw ing n ot to s c ale
P a rt N u m b e r s u ffix
Product Tracking Code (Summit use)
P roduct T racking C ode (Sum m it use)
48 PIN TQFP PACKAGE Top View NOTICE
28 PIN QFN PACKAGE Top View
Note 1 - This is a Preliminary Information data sheet that describes a Summit product currently in pre-production with limited characterization.. SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user's specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. (c) Copyright 2002 SUMMIT Microelectronics, Inc. Power Management for CommunicationsTM Revision 2.0 - This Document supersedes all previous versions.
I2C is a trademark of Philips Corporation.
SUMMIT MICROELECTRONICS, Inc. 2056 2.0 10/04/02
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